Method and system for reconfigurable channel coding

ABSTRACT

Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.

FIELD OF THE INVENTION

[0001] The present invention relates, in general, to channel codingoperations, and more particularly to reconfigurable channel codingoperations to accommodate various wireless communication standards.

BACKGROUND OF THE INVENTION

[0002] The use of cellular telephones in today's society has becomewidespread. While facilitating communication in a myriad ofenvironments, the various existing and emerging wireless standardsinhibit the ability to utilize a single device across the standards andplatforms. The inability to have cross-platform coverage in a singledevice is due in large part to the inability to provide a hardwaresolution that can be adapted to varying standards.

[0003] For example, in terms of the channel coding operations that arenecessary, existing and emerging wireless standards utilize myriad errormitigation techniques to operate in a hostile channel environment.Existing standards utilize two levels of coding plus block interleavingto address both single error and burst error phenomena. Group codes areused for the outer codes, and convolutional codes are used for the innercodes of the various concatenated coding schemes. No two standardsemploy the same combination. Additionally, certain standards employencryption to offer a degree of privacy and security.

[0004] Utilization of an ASIC (application specific integrated circuit)approach for channel coding would be inefficient in such an environment,since there would need to have individual ASICs for supporting eachpossible standard. In addition, there would be an ongoing requirement tosupport modifications from an original design without the ability ofhaving new silicon. A RISC (reduced instruction set computing) option isinefficient for the bit-oriented operations required for channel coding.Similarly, a DSP (digital signal processing) approach is also ill-suitedto the bit-oriented requirements of channel coding. Use of amicroprogrammed approach provides an arcane nature of programming andmaintaining that precludes serious consideration as a solution. WhileFPGAs (field programmable gate arrays) do provide flexibility, the highcosts, both in transistor count and control overhead, outweigh theirbenefits.

[0005] Accordingly, a need exists for a channel coding approach thatallows convenient, efficient, and effective support across multiplestandards. The present invention addresses such a need.

SUMMARY OF THE INVENTION

[0006] Aspects of a reconfigurable system for providing channel codingin a wireless communication device are described. The aspects include aplurality of computation elements for performing channel codingoperations and memory for storing programs to direct each of theplurality of computation elements. A controller controls the pluralityof computation elements and stored programs to achieve channel codingoperations in accordance with a plurality of wireless communicationstandards. The plurality of computation elements include a datareordering element, a linear feedback shift register (LFSR) element, aconvolutional encoder element, and a Viterbi decoder element.

[0007] With the present invention, a reconfigurable channel coder isprovided that minimizes point designs, i.e., the present inventionavoids designs that satisfy a singular requirement of one, and only one,wireless standard, which would render them useless for any otherfunction. Further, bit-oriented operations of channel coding aresuccessfully mapped onto a set of byte-oriented memory and processingelements. In addition, the present invention achieves a channel coder ina manner that provides realizability, reliability, programmability,maintainability, and understand-ability of design, while gaining savingsin power and die area. Numerous other advantages and features of thepresent invention will become readily apparent from the followingdetailed description of the invention and the embodiments thereof, fromthe claims and from the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a block diagram illustrating an adaptive computingengine.

[0009]FIG. 2 is a block diagram illustrating a reconfigurable matrix, aplurality of computation units, and a plurality of computationalelements of the adaptive computing engine.

[0010]FIG. 3 illustrates a block diagram of a channel coding computationunit in accordance with the present invention.

[0011] FIGS. 4-8 each illustrate aspects of computation elements of thechannel coding computation unit of FIG. 3 in accordance with the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0012] While the present invention is susceptible of embodiment in manydifferent forms, there are shown in the drawings and will be describedherein in detail specific embodiments thereof, with the understandingthat the present disclosure is to be considered as an exemplification ofthe principles of the invention and is not intended to limit theinvention to the specific embodiments illustrated.

[0013] The present invention provides aspects of a reconfigurablechannel coder. In a preferred embodiment, the reconfigurable channelcoder is provided as a reconfigurable matrix in accordance with thedescription in co-pending U.S. patent application, Ser. No. ______,entitled “______”, assigned to the assignee of the present invention andincorporated by reference in its entirety herein. Portions of thatdescription are reproduced herein for clarity of presentation of theaspects of the present invention.

[0014] Referring to FIG. 1, a block diagram illustrates an adaptivecomputing engine (“ACE”) 100, which is preferably embodied as anintegrated circuit, or as a portion of an integrated circuit havingother, additional components. In the preferred embodiment, and asdiscussed in greater detail below, the ACE 100 includes a controller120, one or more reconfigurable matrices 150, such as matrices 150Athrough 150N as illustrated, a matrix interconnection network 110, andpreferably also includes a memory 140.

[0015] A significant departure from the prior art, the ACE 100 does notutilize traditional (and typically separate) data and instruction bussesfor signaling and other transmission between and among thereconfigurable matrices 150, the controller 120, and the memory 140, orfor other input/output (“I/O”) functionality. Rather, data, control andconfiguration information are transmitted between and among theseelements, utilizing the matrix interconnection network 110, which may beconfigured and reconfigured, in real-time, to provide any givenconnection between and among the reconfigurable matrices 150, thecontroller 120 and the memory 140, as discussed in greater detail below.

[0016] The memory 140 may be implemented in any desired or preferred wayas known in the art, and may be included within the ACE 100 orincorporated within another IC or portion of an IC. In the preferredembodiment, the memory 140 is included within the ACE 100, andpreferably is a low power consumption random access memory (RAM), butalso may be any other form of memory, such as flash, DRAM, SRAM, MRAM,ROM, EPROM or E²PROM. In the preferred embodiment, the memory 140preferably includes direct memory access (DMA) engines, not separatelyillustrated.

[0017] The controller 120 is preferably implemented as a reducedinstruction set (“RISC”) processor, controller or other device or ICcapable of performing the two types of functionality discussed below.The first control functionality, referred to as “kernal” control, isillustrated as kernal controller (“KARC”) 125, and the second controlfunctionality, referred to as “matrix” control, is illustrated as matrixcontroller (“MARC”) 130.

[0018] The various matrices 150 are reconfigurable and heterogeneous,namely, in general, and depending upon the desired configuration:reconfigurable matrix 150A is generally different from reconfigurablematrices 150B through 150N; reconfigurable matrix 150B is generallydifferent from reconfigurable matrices 150A and 150C through 150N;reconfigurable matrix 150C is generally different from reconfigurablematrices 150A, 150B and 150D through 150N, and so on. The variousreconfigurable matrices 150 each generally contain a different or variedmix of computation units (200, FIG. 2), which in turn generally containa different or varied mix of fixed, application specific computationalelements (250, FIG. 2), which may be connected, configured andreconfigured in various ways to perform varied functions, through theinterconnection networks. In addition to varied internal configurationsand reconfigurations, the various matrices 150 may be connected,configured and reconfigured at a higher level, with respect to each ofthe other matrices 150, through the matrix interconnection network 110.

[0019] Referring now to FIG. 2, a block diagram illustrates, in greaterdetail, a reconfigurable matrix 150 with a plurality of computationunits 200 (illustrated as computation units 200A through 200N), and aplurality of computational elements 250 (illustrated as computationalelements 250A through 250Z), and provides additional illustration of thepreferred types of computational elements 250. As illustrated in FIG. 2,any matrix 150 generally includes a matrix controller 230, a pluralityof computation (or computational) units 200, and as logical orconceptual subsets or portions of the matrix interconnect network 110, adata interconnect network 240 and a Boolean interconnect network 210.The Boolean interconnect network 210, as mentioned above, provides thereconfigurable interconnection capability between and among the variouscomputation units 200, while the data interconnect network 240 providesthe reconfigurable interconnection capability for data input and outputbetween and among the various computation units 200. It should be noted,however, that while conceptually divided into reconfiguration and datacapabilities, any given physical portion of the matrix interconnectionnetwork 110, at any given time, may be operating as either the Booleaninterconnect network 210, the data interconnect network 240, the lowestlevel interconnect 220 (between and among the various computationalelements 250), or other input, output, or connection functionality.

[0020] Continuing to refer to FIG. 2, included within a computation unit200 are a plurality of computational elements 250, illustrated ascomputational elements 250A through 250Z (collectively referred to ascomputational elements 250), and additional interconnect 220. Theinterconnect 220 provides the reconfigurable interconnection capabilityand input/output paths between and among the various computationalelements 250. As indicated above, each of the various computationalelements 250 consist of dedicated, application specific hardwaredesigned to perform a given task or range of tasks, resulting in aplurality of different, fixed computational elements 250. The fixedcomputational elements 250 may be reconfigurably connected together toexecute an algorithm or other function, at any given time, utilizing theinterconnect 220, the Boolean network 210, and the matrixinterconnection network 110.

[0021] In the preferred embodiment, the various computational elements250 are designed and grouped together, into the various reconfigurablecomputation units 200. In addition to computational elements 250 whichare designed to execute a particular algorithm or function, such asmultiplication, other types of computational elements 250 may also beutilized. As illustrated in FIG. 2, computational elements 250A and 250Bimplement memory, to provide local memory elements for any givencalculation or processing function (compared to the more “remote” memory140). In addition, computational elements 2501, 250J, 250K and 250L areconfigured (using, for example, a plurality of flip-flops) to implementfinite state machines, to provide local processing capability (comparedto the more “remote” MARC 130), especially suitable for complicatedcontrol processing.

[0022] In the preferred embodiment, a matrix controller 230 is alsoincluded within any given matrix 150, to provide greater locality ofreference and control of any reconfiguration processes and anycorresponding data manipulations. For example, once a reconfiguration ofcomputational elements 250 has occurred within any given computationunit 200, the matrix controller 230 may direct that that particularinstantiation (or configuration) remain intact for a certain period oftime to, for example, continue repetitive data processing for a givenapplication.

[0023] With the various types of different computational elements 250which may be available, depending upon the desired functionality of theACE 100, the computation units 200 may be loosely categorized. A firstcategory of computation units 200 includes computational elements 250performing linear operations, such as multiplication, addition, finiteimpulse response filtering, and so on. A second category of computationunits 200 includes computational elements 250 performing non-linearoperations, such as discrete cosine transformation, trigonometriccalculations, and complex multiplications. A third type of computationunit 200 implements a finite state machine, such as computation unit200C as illustrated in FIG. 2, particularly useful for complicatedcontrol sequences, dynamic scheduling, and input/output management,while a fourth type may implement memory and memory management, such ascomputation unit 200A. Lastly, a fifth type of computation unit 200 maybe included to perform bit-level manipulation.

[0024] The operations of channel coding fall within this fifth categorytype for computation unit 200. An overall diagram of a channel codingcomputation unit in accordance with the present invention that performsacross standards in a flexible and reliable manner is shown in FIG. 3.The channel coding computation unit/channel coder 310 includes aplurality of configurable and/or programmable memory and processingelements and has three principle interfaces: a front end or upstreaminterface 312, a Vocoder or downstream interface 314, and a hostinterface 316. The channel coder 310 receives demodulated symbols fromthe RECEIVE segment of the upstream interface 312 via the shift register318 and sends modulation symbols to the TRANSMIT segment of the upstreaminterface 312 via the shift register 320. Upstream shared memory 322 anddownstream shared memory 324 provide ping/pong pairs of buffer memoriesfor the data interfaces. Data blocks are transferred at a fixed rate,e.g., one block in each direction every 20 milliseconds.

[0025] For example, for the receive path, during one 20 millisecondinterval, data from the front-end interface 312 is written into thereceive PING buffer memory and data in the receive PONG buffer memory isprocessed by the channel coder 310. During the next 20 millisecondinterval, data from the front-end interface 312 is written into thereceive PONG buffer memory and data in the receive PING buffer memory isprocessed by the channel coder 310, and so on. A pair of control signalssynchronizes these operations, where one indicates the beginning of eachinterval and the other indicates the ping/pong state. These operationsare performed similarly with a second pair of buffer memories used inthe transmit path.

[0026] The channel coder 310 sends speech blocks to a vocoder decoder(not shown) and receives speech blocks from a vocoder encoder (notshown) via the downstream interface 314. Again, ping/pong buffers areutilized for the transmit and receive operations via the downstreaminterface 314 with memory 324. Thus, for example, during one 20millisecond interval, data from the channel coder 310 is written into aPING buffer memory and data in the PONG buffer memory is processed bythe vocoder decoder. During the next 20-millisecond interval, data fromthe channel coder 310 is written into the PONG buffer memory and data inthe PING buffer memory is processed by the vocoder decoder, and so on.Three control signals synchronizes these operations, where one indicatesthe beginning of each interval, a second indicates the ping/pong state,and a third indicates valid/corrupted data for the receive path only.These operations are performed similarly with a second pair of buffermemories used for the data interface between the channel coder andvocoder encoder. Continuing to refer to FIG. 3, there are severalinterfaces between the host controller 120 and channel coder 310 thatprovide the host interface 316. One supports the configuration of thechannel coder 310 and another is used for control and status. The third,denoted as downstream/host shared memory 324, provides bidirectionalmessage transfer between the channel coder's 310 physical layer and thehigher protocol layers executing on the host controller 120.

[0027] For many of the channel coding operations of channel coder 310,reordering and/or randomly accessing the bits that comprise a data blockare required. For example, for the GSM standard, 260 bit blocks of dataare generated by the speech encoder every 20 milliseconds. These bitsare manipulated three different ways before they are transmitted, as iswell understood in the art. First, the most perceptually significant 50bits from each 260 bit block must be accessed in a nearly random fashionand input to a CRC generator. Next, 182 bits from the 260 bit block, the3 CRC bits, and four tail bits are reordered for input to a R=½convolutional encoder. Finally, the remaining least perceptuallysignificant 78 bits from the 260 bit block and the 378 bits from theR={fraction (1/2)} convolutional encoder are reordered into eight 57-bitblocks, employing an interleaving algorithm for burst error mitigation.

[0028] Each of the other standards also requires data reorderingoperations, but the implementation details vary widely. Two generalclasses of reordering are required. One class can be describedalgorithmically, while a second class basically requires random accesscapability. An interleaver is an example of the former, and bit pickingfrom the encoded speed blocks is an example of the latter. In order toachieve both classes of reordering while avoiding point solutions, thechannel coder 310 of the present invention employs a look-up tableapproach, as described with reference to FIG. 4.

[0029]FIG. 4 illustrates an example of a reordering element 330 as acomputation element of the channel coder 310 in accordance with thepresent invention. The byte-wide organization supports arbitraryreordering of 256-bit data blocks. In operation, an up counter 332 isincremented from 0 to N−1, where N represents the length of the datavector. For this example, Nmax is 256. For each count, the look-up tablememory 334 outputs an encoded byte that contains the location of thedesired bit in the 32-byte source data memory 336. Five bits specify thebyte memory address and three bits indicate the desired 1-of-8 data bitsfrom multiplexer 338. The desired bit is stored in the stager 340, e.g.,an 8-bit serial-in, parallel-out shift register. The staged bytes arewritten sequentially into the 32-byte sink data memory 342.

[0030] Of course, the reordering element 330 also supports random accessoperations. For example, the GSM standard requires the random access of50 bits of encoded speech deemed most perceptually significant for thepurpose of generating CRC protection. For random access operations,however, data is not moved from a source memory 336 to a sink memory342. Thus, only the top four blocks 332, 334, 336, and 338 are required.

[0031] While the reordering element 330 has been described in terms of256-bit data block size, in order to handle data blocks larger than 256bits, the look-up table width has to be greater than eight bits. Anextension of the look-up table memory width would accommodate a greaterwidth. Alternatively, two bytes could be processed per bit.

[0032] In addition to reordering data, channel coding schemes normallyinclude error detecting cyclic codes, error detecting and correctingHamming codes, single burst error correcting Fire codes, and so on.Typically, these codes are represented by their generator polynomials.The degree of polynomials used for the various wireless standards spansa wide range, from degree 3 for a GSM CRC, to degree 42 for the CDMAlong code, to effective degrees of 64 and 128 for the GSM and Bluetoothciphers, respectively. While separate encoders and decoders can beimplemented for each of these standards utilizing linear feedback shiftregisters (LFSRs), the channel coder 310 implements a programmablespecial purpose computational element to perform the operations of aLFSR that accommodates the various standards as needed. Normally, LSFRsare bit-oriented structures which combine shift register stages andmod-2 adders. The present invention provides a programmable,byte-oriented structure, as represented in the block diagram of FIG. 5.

[0033] By way of example, the generator polynomial used for GSM (224,184) Fire code is g(x)=x⁴⁰+x²⁶+x²³+x¹⁷+x³+1. A block of 184 bits isprotected by 40 extra parity bits used for error detection andcorrection. These bits are appended to the 184 bits to form a 224 bitsequence. In order to map bit-oriented encoder operations onto thebyte-oriented LFSR element of the present invention, the processing ofeight information bits at one time and the computing the LFSR stateafter eight consecutive shifts are required.

[0034] Referring now to FIG. 5, a byte-oriented memory (not shown)contains the information bytes, with five bytes representing the fortybit LFSR data. For the structure shown in FIG. 5, the feedback byte iscomputed and stored in a register (REG) 350, while the computationoccurs through the use of a shifter 352, multiplexer 354, exclusive-ORgate (XOR) 356, and accumulator (ACC) 358 in accordance with thefollowing pseudo code. In the notation used, REG_R(k) represents alogical right shift of the feedback byte by k positions for k=1 to 7,while REG_L(k) represents a logical left shift of the feedback byte by kpositions for k=1 to 7. The information byte is represented as d[0:7],and the five LSFR bytes are represented with LSFR[39:32], LFSR[31:24],LFSR[23:16], LFSR[15:8], and LFSR[7:0]. The sixteen possible outputsfrom the shifter element 352 are represented in FIG. 6. The LSFR valuesare set to zero for the first iteration.

[0035] 1. Compute the Feedback Byte

[0036] (e.g.,

[0037] REG←d[0:7]

[0038] REG←REG⊕LFSR[39:32])

[0039] 2. Update the five LFSR bytes

[0040] (e.g.,

[0041] ACC←LFSR[31:24]

[0042] LFSR[39:32]←ACC⊕REG_R(6)

[0043] ACC←LFSR[23:16]←REG_R(7)

[0044] ACC←ACC⊕REG_R(1)

[0045] LFSR[31:24]←ACC⊕REG_L(2)

[0046] ACC←LFSR[15:8]⊕REG_L(1)

[0047] LFSR[23:16]←ACC⊕REG_L(7)

[0048] ACC←LFSR[7:0]⊕REG_R(5)

[0049] LFSR[15:8]←ACC

[0050] ACC←REG

[0051] LFSR[7:0]←ACC⊕REG_L(3))

[0052] 3. Repeat routine as needed

[0053] (e.g.,

[0054] The routine is repeated 23 times to process the 184 informationbits (23 information bytes).)

[0055] In addition to LSFR operations, the channel coder 310 alsoperforms the processing necessary for the various wireless standardsthat employ convolutional codes for the inner codes of theirconcatenated coding schemes. Typically, a convolutional encoder will berepresented by its constraint length (k), rate (R=m/n, denoting theencoding of ‘m’ message symbols into ‘n’ coded symbols, and generatorpolynomials that describe the connections between a k-stage shiftregister and modulo-2 adders, as is well understood in the art.

[0056] In accordance with the present invention, a byte-oriented,special purpose computational element interfaced to a byte-wide memoryand a simple load/store-type programming model performs the encodingfunction for all of the convolutional codes identified below in thechannel coder 310. FIG. 7 illustrates the convolutional encoder elementin accordance with the present invention that can perform encodingfunctions for convolutional codes, including:

[0057] the GSM standard rate 1/2, constraint length

G0=1+D ³ +D ⁴

G1=1+D+D ³ +D ⁴;

[0058] the IS-136 TDMA rate ½, constraint length 6

G0=1+D+D ³ +D ⁵

G1=1+D ² +D ³ +D ⁴ +D ⁵

[0059] the IS-136 TDMA rate ¼, constraint length 6

G0=1 +D+D³ +D ⁴ +D ⁵

G1=1+D+D ² +D ⁵

G2=1+D+D ² +D ³ +D ⁵

G3=1+D ² +D ⁴ +D ⁵;

[0060] the IS-95 CDMA rate ⅓ constraint length 9

G0=1+D ² +D ³ +D ⁵ +D ⁶ +D ⁷ +D ⁸

G1=1+D+D ³ +D ⁴ +D ⁷ +D ⁸

G2=1+D+D ² +D ⁵ +D ⁸; and

[0061] the IS-95 CDMA rate ½, constraint length 9

G0=1+D+D ² +D ³ +D ⁵ +D ⁷ +D ⁸

G1=1+D ² +D ³ +D ⁴ +D ⁸.

[0062] As shown in FIG. 7, the convolutional element supports theseconvolutional codes through polynomial generators 370, each of whichincludes a configuration register 372 that receives configuration datafrom the host controller 120, provides that data to an AND component 374for logical combination with delay data from a delay register 376, theresult of which gets logically combined with the delay data via an XORcomponent 378. Selection of an appropriate output from the polynomialgenerators 370 is performed via a multiplexer 380 controlled by a rateselector 382. The output of the multiplexer 380 then gets shifted via ashift register 384 and sent to memory. With the convolutional encodershown in FIG. 7, the channel coder 310 of the present invention supportsall rate ½, ⅓, and ¼ convolutional codes, any constraint length up tok=9, and arbitrary puncturing.

[0063] These convolutional codes are decoded usually with a simpleiterative process known as the Viterbi algorithm, where a Viterbidecoder determines the encoder state using a maximum likelihoodtechnique. To determine the encoder state, the Viterbi algorithmnormally generates a set of 2^((k−1)) state metrics that measure theoccurrence probability for each of the ₂(k-1) possible encoder states.As the state metrics are computed, a decision is formed for each of the2^((k−1)) possible states to determine the probable path taken to arriveat that particular state. These decisions are stored in a path memorythat is traced backward to generate the decoded output.

[0064] A Trellis structure is a common method for representing aconvolutional encoder's state transitions over time. The convention isthat an input ‘0’ corresponds to the selection of the upper branch, andan input ‘1’ corresponds to the selection of the lower branch. Eachpossible input sequence corresponds to a particular path through thetrellis.

[0065] The Viterbi algorithm compares the two paths entering each nodeand retains only the path with the better metric. The other path isdiscarded, since its likelihood never can exceed that of the retainedpath no matter what data are subsequently received. The retained pathsare called survivors.

[0066] Commonly, the computational element of a Viterbi decoder iscalled an Add-Compare-Select (ACS) unit, since it consists of adders,comparators, and selectors. It is used to update a set of path metricsfor the surviving hypotheses by adding appropriate branch metrics to thepath metrics of the precursor hypotheses.

[0067] A block diagram of a Viterbi decoder computation element ofchannel coder 310 in accordance with the present invention isillustrated in FIG. 8. As illustrated, the Viterbi decoder elementincludes a counter 400, codeword and punctures look-up table (LUT) 402,register 404, recode logic 406, an address generator 408, path metricsmemory 410, state registers 412 and 414, plus/minus adjusters 416,adders 418, selector 420, and comparator 422. In operation, thesecomponents of the Viterbi decoder computation element compute pairs ofsurvivor path metrics by adding appropriate branch metrics to pairs ofprecursor path metrics. The sums are compared, and the better (lower)results are selected. The element performs the memory-to-memory,in-place algorithm. Survivor path bits are aggregated into bytes, storedin byte memory, and subsequently backward path-traced to generate thedecoder output.

[0068] For the branch metrics, the Hamming distance between the receivedword and the code words, i.e., the sums of the bit-wise mismatchesbetween the received words and the code words, are used. For rate ½, ⅓,and ¼ codes, received words and code words will consist of two, three,and four bits, respectively. For punctured codes, stored tables are usedto indicate the punctured bits that are disregarded in the branch metriccomputation.

[0069] The range of the branch metrics (mb) is 0 to 4. For a maximumcode constraint length of k=9, the maximum metric range need not exceedmb·(k−1)=4×8=32. Using eight bit two's complement arithmetic, the branchmetrics range can be increased, if necessary, as is well appreciated bythose skilled in the art.

[0070] With the Viterbi decoder shown in FIG. 8 along with the othercomputational elements described with reference to FIGS. 4-7, thechannel coder of FIG. 3 is realized in a manner that achieves theability to be reconfigured and adapted, as needed, to various wirelessstandards and their different approaches to channel coding operations.From the foregoing, it will be observed that numerous variations andmodifications may be effected without departing from the spirit andscope of the novel concept of the invention. It is to be understood thatno limitation with respect to the specific methods and apparatusillustrated herein is intended or should be inferred. It is, of course,intended to cover by the appended claims all such modifications as fallwithin the scope of the claims.

What is claimed is:
 1. A reconfigurable system for providing channelcoding in a wireless communication device comprising: a plurality ofcomputation elements for performing channel coding operations; memoryfor storing programs to direct each of the plurality of computationelements; and a controller for controlling the plurality of computationelements and stored programs to achieve channel coding operations inaccordance with a plurality of wireless communication standards.
 2. Thereconfigurable system of claim 1 further comprising a host controllerfor reconfiguring the channel coding by providing programs that updatethe stored programs to accommodate a change in the wireless standard. 3.The reconfigurable system of claim 1 wherein each of the plurality ofcomputation elements further comprises a finite state machine.
 4. Thereconfigurable system of claim 1 wherein the plurality of computationelements further comprises a data reordering element.
 5. Thereconfigurable system of claim 4 wherein the data reordering elementfurther comprises a coupled configuration of a counter, a look-up table,a data input source, a multiplexer, a stager, and a data output source.6. The reconfigurable system of claim 4 wherein the plurality ofcomputation elements further comprises a linear feedback shift register(LFSR) element.
 7. The reconfigurable system of claim 6 wherein the LFSRelement further comprises a coupled configuration of a register, ashifter, a multiplexer, a exclusive-OR logic means, and an accumulator.8. The reconfigurable system of claim 7 wherein the LFSR elementoperates in a byte-oriented manner.
 9. The reconfigurable system ofclaim 6 wherein the plurality of computation elements further comprisesa convolutional encoder element.
 10. The reconfigurable system of claim9 wherein the convolutional encoder further comprises a coupledconfiguration of an input shift register, a delay register, a pluralityof polynomial generators, a rate selector means, a multiplexer, and anoutput shift register.
 11. The reconfigurable system of claim 10 whereineach of the plurality of polynomial generators further comprises aconfiguration register, an AND logic means, and an exclusive-OR logicmeans.
 12. The reconfigurable system of claim 11 wherein theconvolutional encoder operates in a byte-oriented manner.
 13. Thereconfigurable system of claim 9 wherein the plurality of computationelements further comprises a Viterbi decoder element.
 14. Thereconfigurable system of claim 13 wherein the Viterbi decoder elementfurther comprises a coupled configuration of a counter, a codeword andpunctures look-up table, a register, recode logic, an address generator,path metrics memory, state registers, plus/minus adjusters, adders, aselector, and a comparator.
 15. A method for achieving channel coding ina wireless communication device that adapts to changes in wirelesscommunication standards, the method comprising: providing a plurality ofcomputation elements for performing channel coding operations; providingmemory for storing programs to direct each of the plurality ofcomputation elements; and providing a controller for controlling theplurality of computation elements and stored programs to achieve channelcoding operations in accordance with a plurality of wirelesscommunication standards.
 16. The method of claim 15 further comprisingproviding a host controller for reconfiguring the channel coding byproviding programs that update the stored programs to accommodate achange in the wireless standard.
 17. The method of claim 15 whereinproviding a plurality of computation elements further comprisesproviding each computation element with a finite state machine.
 18. Themethod of claim 15 wherein providing a plurality of computation elementsfurther comprises providing a data reordering element, a linear feedbackshift register (LFSR) element, a convolutional encoder element, and aViterbi decoder element.
 19. A reconfigurable system for providingchannel coding in a wireless communication device comprising: aplurality of computation units for providing operations for a wirelesscommunication device that adjust to changes in wireless communicationstandards, the plurality of computation units including a channel codercomputation unit; and a host controller for configuring the plurality ofcomputation units based on which of the wireless communication standardsis used in a particular environment.
 20. The reconfigurable system ofclaim 19 wherein the channel coding computation unit further comprises:a plurality of computation elements for performing channel codingoperations; memory for storing programs to direct each of the pluralityof computation elements; and a controller for controlling the pluralityof computation elements and stored programs to achieve channel codingoperations in accordance with the plurality of wireless communicationstandards.
 21. The reconfigurable system of claim 19 wherein each of theplurality of computation elements further comprises a finite statemachine.
 22. The reconfigurable system of claim 19 wherein the pluralityof computation elements further comprises a data reordering element, alinear feedback shift register (LFSR) element, a convolutional encoderelement, and a Viterbi decoder element.